Ld a, r, Operation, Description – Zilog EZ80F916 User Manual
Page 202: Condition bits affected attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
193
LD A, R
Load Accumulator
Operation
A R
Description
The CPU writes the contents of the Refresh Counter register, R, to the accumulator, A.
Condition Bits Affected
Attributes
S
Set if the R register is negative; reset otherwise.
Z
Set if the R register is 0; reset otherwise.
H
Reset.
P/V
Contains contents of IEF2.
N
Reset.
C
Not affected.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
LD
A,I
X
2
ED, 5F
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