Ini2r, Operation, Description – Zilog EZ80F916 User Manual
Page 182: Condition bits affected attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
173
INI2R
Input from I/O and Increment with Repeat
Operation
repeat {
(HL) ({UU, DE[15:0]})
BC BC – 1
DE DE+1
HL HL+1
} while BC 0
Description
The CPU places the contents of DE[15:0] onto the lower two bytes of the address bus,
ADDR[15:0], and places a 0 onto the upper byte of the address bus, ADDR[23:16]. The
CPU reads the byte at this I/O address into CPU memory. The CPU next places the con-
tents of HL onto the address bus and writes the byte to the memory address specified by
the HL register. The BC register decrements. The DE and HL registers increment. Next,
the CPU sets the Z Flag to 1 if the BC register decrements to 0. The instruction repeats
until the BC register equals 0.
Condition Bits Affected
Attributes
S
Not affected.
Z
Set if BC – 1 = 0; reset otherwise.
H
Not affected.
P/V
Not affected.
N
Set if msb of data is a logical 1; reset otherwise.
C
Not affected.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
INI2R
—
X
2
+
3
*
BC
ED, 94
INI2R.S
—
1
3
+
3
*
BC
52, ED, 94
INI2R.L
—
0
3
+
3
*
BC
49, ED, 94