Zilog EZ80F916 - Manual (Page 236)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
227
LD r, r’
Load Register
Operation
r
 r’
Description
The r and r’ operands are any of A, B, C, D, E, H, or L. The CPU writes the contents of
the r’ register to the r register. The r’ register described here should not be confused with
the registers in the alternate working register set.
Condition Bits Affected
None.
Attributes
jj
= binary code
01 ddd sss
where
ddd
identifies the destination A, B, C, D, E, H, or L
register and
sss
identifies the source A, B, C, D, E, H, or L register assembled in the
object code, as indicated in Table 70 .
Mnemonic Operand ADL Mode Cycle Opcode (hex)
LD r
,r’ X 1
jj
Table 70. Register and jj Opcodes for LD r, r’ Instruction (hex)
Register jj (ddd or sss)
A
111
B
000
C
001
D
010
E
011
H
100
L
101