Zilog EZ80F916 - Manual (Page 69)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
60
BIT
b,s
Z  ~s[b]
(HL)
CB 46–7E
X * 1 X 0 —
(IX/Y+d) DD/FD CB dd
46–7E
r CB 40–7F
CALL
cc,Mmn
if cc {
(SP)
 PC
PC  Mmn
}
C4–FC
— — — — — —
CALL
Mmn
(SP)
 PC
PC  Mmn
CD
— — — — — —
CCF
C  ~C
3F
— — * — 0 *
CP
A,s
A – s
(HL)
BE
* * * V 1 *
ir DD/FD BC–BD
(IX/Y+d) DD/FD BE dd
n FE
r B8–BF
CPD
A–(HL)
HL  HL – 1
BC  BC – 1
ED A9
* * * * 1 —
CPDR
repeat {
A–(HL)
HL  HL – 1
BC  BC – 1
} while (~Z and BC  0)
ED B9
* * * * 1 —
Table 37. Instruction Summary (Continued)
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source S Z H P/V N C
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.