47 for d, Operation, Description – Zilog EZ80F916 User Manual
Page 156: Condition bits affected, Attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
147
EXX
Exchange Working Register Set with Alternate Register Set
Operation
BC BC’
DE DE’
HL HL’
Description
The CPU exchanges the contents of the primary working registers BC, DE, and HL with
the alternate working registers BC’, DE’, and HL’, respectively.
Condition Bits Affected
None.
Attributes
Mnemonic
Operand
ADL Mode
Cycle
Opcode (hex)
EXX
—
X
1
D9
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