Zilog EZ80F916 - Manual (Page 83)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
74
RLC s
(HL)
CB 06
* * 0 P 0 *
(IX/Y+d)
DD/FD CB dd
06
r CB 00-07
RLCA
A
07
— — 0 — 0 *
RLD
A[3:0]  (HL)[7:4]
(HL)[7:4]  (HL)[3:0]
(HL)[3:0]  A[3:0]
ED 6F
* * 0 P 0 —
RR s
(HL)
CB 1E
* * 0 P 0 *
(IX/Y+d)
DD/FD CB dd
1E
r CB 18-1F
RRA
A
1F
— — 0 — 0 *
Table 37. Instruction Summary (Continued)
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source S Z H P/V N C
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.
C
7 0
A
3 7 4 0 3 7 4 0 (HL) A
CY 7 0
A
C
7 0
s
C 7 0
s