Zilog EZ80F916 - Manual (Page 142)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
133
DEC ir
Decrement
Operation
ir
 ir – 1
Description:
The ir operand is any of 8-bit CPU registers IXH, IXL, IYH, or IYL. The value contained
in the specified register is decremented by 1.
Condition Bits Affected
Attributes
S
Set if result is negative; reset otherwise.
Z
Set if result is 0; reset otherwise.
H
Set is borrowed from bit 4; reset otherwise.
P/V
Set if operand was 80h before operation; reset otherwise.
N
Set.
C
Not affected.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
DEC
IXH X 2
DD, 25
DEC
IXL X 2
DD, 2D
DEC
IXH X 2
FD, 25
DEC
IXL X 2
FD, 2D