Zilog EZ80F916 - Manual (Page 49)

eZ80
®
CPU
User Manual
UM007715-0415 Interrupts
40
Interrupt Mode 1
In Interrupt Mode 1, the CPU responds to an interrupt by executing a restart to location
0038h
(RST
38h
). Interrupt Mode 1 is selected by executing a IM 1 instruction.
ADL mode 1 1 Read RST n or CALL Mmn instruction placed on the
data bus, D[7:0], by interrupting peripheral.
IEF1
 0
IEF2
 0
The starting program counter is PC[23:0]. Push the 3-
byte return address, PC[23:0], onto the SPL stack.
Push a 03h byte onto the SPL stack, indicating an
interrupt from ADL mode (because ADL = 1). The ADL
mode bit remains set to 1. Write {0000h, nn} or {MM,
mm, nn} to PC[23:0]. The ending program counter is
PC[23:0] = {0000h, nn} or {MM, mm, nn}. The interrupt
service routine must end with RETI.L
Table 23. Interrupt Mode 1 Operation
Current
Memory Mode
ADL
Mode
Bit MADL
Control
Bit
Operation
Z80 mode 0 0
IEF1
 0
IEF2
 0
The starting program counter is {MBASE, PC[15:0]}.
Push the 2-byte return address, PC[15:0], onto the
{MBASE,SPS} stack. The ADL mode bit remains
cleared to 0. Write 0038h to PC[15:0]. The ending
program counter is {MBASE, PC[15:0]} = {MBASE,
0038h
} The interrupt service routine must end with
RETI
.
ADL mode 1 0
IEF1
 0
IEF2
 0
The starting program counter is PC[23:0]. Push the 3-
byte return address, PC[23:0], onto the SPL stack. The
ADL mode bit remains set to 1. Write 000038h to
PC[23:0]. The ending program counter is
PC[23:0] = 000038h. The interrupt service routine must
end with RETI.
Table 22. Interrupt Mode 0 Operation (Continued)
Current
Memory Mode
ADL
Mode
Bit MADL
Control
Bit
Operation (if RST n or CALL Mmn is placed on the
data bus)