Zilog EZ80F916 - Manual (Page 407)

UM007715-0415 Index
eZ80
®
CPU
User Manual
398
Load Register 221, 222, 224, 226, 227, 228, 229,
230, 231
Load Stack Pointer 234, 235, 236, 237
Logical AND 100, 101, 102, 103, 104
Logical Exclusive OR 368, 369, 370, 372, 373
Logical OR 250, 251, 252, 253, 254
LSB and MSB, Use of the Terms ix
M
MADL 10, 388
MADL bit flag 14, 75, 76, 325, 356
MADL control bit 34, 292, 294, 297, 298, 300, 301
MADL single-bit flag 12, 13
Main Register Set 11, 13
main register set 9
Manual Conventions vii
Manual Objectives vi
Manual Organization vi
Maskable Interrupt 38
maskable interrupt 36
maskable interrupt mode 38
MBASE address register 6, 7, 10
MBASE register 3, 7, 9, 10, 11, 48
MBASE register, Load MBASE instruction 215
memory addressing modes 48
MIXED MEMORY mode 46
MIXED MEMORY Mode Guidelines 34
Mixed-ADL Bit 10, 388
mixed-memory mode applications 41, 44
MLT rr 246
MLT SP 247
Mode Control 3
Mode Control block 3
Multiply Register 246
Multiply Stack Pointer 247
N
NEG 248
Negate Accumulator 248
NMI 36
No Operation 249
nonmaskable interrupt 36, 58, 300, 391
Nonmaskable Interrupt Operation 37
Nonmaskable Interrupt, Return from 300
NOP 249
O
Op Code Decoder 3
Op Code maps 375
Op Code Suffixes for Memory Mode Control 18
Op Codes, instruction fetch of 2
operands, instruction fetch of 2
OR A, (HL) 250
OR A, (IX/Y + d) 252
OR A, ir 251
OR A, n 253
OR A, r 254
OTD2R 256
OTDM 258
OTDMR 259
OTDR 260
OTDRX 261
OTI2R 262
OTIM 264
OTIMR 265
OTIR 266
OTIRX 267
OUT (BC) 268
OUT (n), A 269
OUT instruction 47, 51
OUT0 (n), r 270
OUTD 271
OUTD2 272
OUTI 273
OUTI2 274
Output to I/O 268, 269, 270
Output to I/O and Decrement 258, 259, 260, 271,
272
Output to I/O and Decrement with Repeat 256
Output to I/O and Increment 264, 265, 266, 273,
274
Output to I/O and Increment with Repeat 262
P
Parentheses viii
Parentheses/Bracket Combinations viii
Parity flag 36
Parity/Overflow Flag 15, 390