Indm, Operation, Description – Zilog EZ80F916 User Manual
Page 176: Condition bits affected attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
167
INDM
Input from I/O and Decrement
Operation
(HL) ({UU, 00h, C})
B B – 1
C C – 1
HL HL – 1
Description
The CPU places the contents of register C onto the lower byte of the address bus,
ADDR[7:0]. The upper byte of the address bus, ADDR[23:16] is undefined for I/O
addresses. The CPU reads the byte located at this I/O address into CPU memory. The CPU
next places the contents of HL onto the address bus and writes the byte to the memory
address specified by the HL register. Next, the CPU decrements the B, C, and HL regis-
ters, and sets the Z Flag to 1 if the B register is decremented to 0.
Condition Bits Affected
Attributes
S
Undefined.
Z
Set if B – 1 = 0; reset otherwise.
H
Undefined.
P/V
Undefined.
N
Set if msb of data is a logical 1; reset otherwise.
C
Undefined.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
INDM
—
X
5
ED, 8A
INDM.S
—
1
6
52, ED, 8A
INDM.L
—
0
6
49, ED, 8A