Zilog EZ80F916 - Manual (Page 39)

eZ80
®
CPU
User Manual
UM007715-0415 Memory Mode Switching
30
RST.S
n 1
RST.SIL
n
assembles to
52 CD nn
The starting program counter is PC[23:0]. Push the
2 LS bytes of the return address, PC[15:0], onto
the {MBASE, SPS} stack. Push the MS byte of the
return address, PC[23:16], onto the SPL stack.
Push a 03h byte onto the SPL stack, indicating an
interrupt from ADL mode (because ADL = 1 ). Reset
ADL mode bit to 0. Write {00h, nn} to PC[15:0].
The ending program counter is {MBASE,
PC[15:0]} = {MBASE, 00h, nn}.
RST.L
n 0
RST.LIS
n
assembles to
49 CD nn
The starting program counter is {MBASE,
PC[15:0]}. Push the 2-byte return address,
PC[15:0], onto the SPL stack. Push a 02h byte
onto the SPL stack, indicating an interrupt from
Z80 mode (because ADL = 0) . Set the ADL mode
bit to 1. Write {0000h, nn} to PC[23:0]. The ending
program counter is PC[23:0] = {0000h, nn}.
RST.L
n 1
RST.LIL
n
assembles to
5B CD nn
The starting program counter is PC[23:0]. Push the 
3-byte return address, PC[23:0], onto the SPL
stack. Push a 03h byte onto the SPL stack,
indicating an interrupt from ADL mode (because
ADL = 1). The ADL mode bit remains set to 1. Write
{0000h, nn} to PC[23:0]. The ending program
counter is PC[23:0] = {0000h, nn}.
Table 18. RET Instruction
User Code
ADL
Mode Assembled
Code
Operation
RET
0
RET
assembles to
C9
The starting program counter is {MBASE,
PC[15:0]}. Pop a 2-byte return address from
{MBASE, SPS} into PC[15:0]. The ADL mode bit
remains cleared to 0. The ending program counter
is {MBASE, PC[15:0]}.
RET
1
RET
assembles to
C9
The starting program counter is PC[23:0]. Pop a 3-
byte return address from SPL into PC[23:0]. The
ADL mode bit remains set to 1. The ending
program counter is PC[23:0].
RET.S
0 — An invalid suffix. RET.L must be used in all mixed-
memory mode applications.
Table 17. RST n Instruction (Continued)
User Code
ADL
Mode Assembled
Code
Operation