Zilog EZ80F916 - Manual (Page 281)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
272
OUTD2
Output to I/O and Decrement
Operation
({UU, BC[15:0]})  (HL)
B  B – 1
C  C – 1
HL  HL – 1
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to I/O address {UU, BC[15:0]}. The
upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The B, C, and
HL registers decrement.
Condition Bits Affected
Attributes
S
Not affected.
Z
Set if B – 1 = 0; reset otherwise.
H
Not affected.
P/V
Not affected.
N
Set if msb of data is logical 1; reset otherwise.
C
Not affected.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
OUTD2
— X 5
ED, AC
OUTD2.S
— 1 6
52, ED, AC
OUTD2.L
— 0 6
49, ED, AC