Zilog EZ80F916 - Manual (Page 160)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
151
IN r, (BC)—also IN r, (C) for Z80 compatibility
Input from I/O
Operation
r
 ({UU, BC[15:0]})
Description
The CPU places the contents of the 16-bit BC multibyte register onto the lower two bytes
of the address bus at ADDR[15:0]. The upper byte of the address bus, ADDR[23:16] is
undefined for I/O addresses. The byte located at I/O address {UU, BC[15:0]} is written to
the specified register
r
(A, B, C, D, E, H, or L).
Condition Bits Affected
Attributes
jj
identifies the A, B, C, D, E, H, or L register and is assembled into one of the opcodes
indicated in Table 54 .
S
Set if byte is negative; reset otherwise.
Z
Set if byte is 0; reset otherwise.
H
Reset.
P/V
Set if parity is even; reset otherwise.
N
Reset.
C
Not affected.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
IN r
, (BC) X 3
ED, jj