Ind2r, Operation, Description – Zilog EZ80F916 User Manual
Page 174: Condition bits affected attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
165
IND2R
Input from I/O and Decrement with Repeat
Operation
repeat {
(HL) ({UU, DE[15:0]})
BC BC – 1
DE DE – 1
HL HL – 1
} while BC 0
Description
The CPU places the contents of DE[15:0] onto the lower two bytes of the address bus,
ADDR[15:0]. The upper byte of the address bus, ADDR[23:16], is undefined for I/O
addresses. The CPU reads the byte at this I/O address into CPU memory. The CPU next
places the contents of HL onto the address bus and writes the byte to the memory address
specified by the HL register. Next, the CPU decrements the BC, DE, and HL registers, and
sets the Z Flag to 1 if the BC register is decremented to 0. The instruction repeats until the
BC register equals 0.
Condition Bits Affected
Attributes
S
Not affected.
Z
Set if BC – 1 = 0; reset otherwise.
H
Not affected.
P/V
Not affected.
N
Set if msb of data is a logical 1; reset otherwise.
C
Not affected.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
IND2R
—
X
2
+
3
*
BC
ED, 9C
IND2R.S
—
1
3
+
3
*
BC
52, ED, 9C
IND2R.L
—
0
3
+
3
*
BC
49, ED, 9C