Zilog EZ80F916 - Manual (Page 406)

UM007715-0415 Index
eZ80
®
CPU
User Manual
397
JP (HL) 182
JP (IX/Y) 183
JP cc, Mmn 180
JP Mmn 185
JR cc’, d 187
JR d 188
Jump 52, 58, 185, 385
Jump Indirect 182, 183
Jump instruction 4
Jump instruction, Conditional 180
Jump instruction, Relative Conditional 187
Jump not 0 instruction, Decrement B 141
Jump Relative 188
L
LD (HL), IX/Y 195, 196
LD (HL), n 197
LD (HL), r 198
LD (HL), rr 199
LD (IX/Y + d), IX/Y 210
LD (IX/Y + d), n 211
LD (IX/Y + d), r 212
LD (IX/Y + d), rr 214
LD (Mmn), A 216
LD (Mmn), IX/Y 217
LD (Mmn), rr 218
LD (Mmn), SP 219
LD (rr), A 233
LD A, (IX/Y + d) 190
LD A, (Mmn) 192
LD A, (rr) 194
LD A, I 189, 195
LD A, MB 191
LD A, R 193
LD HL, Mmn in ADL Mode 21
LD HL, Mmn in Z80 Mode 20
LD I, A 201
LD instruction 4, 53
LD ir, ir’ 202
LD ir, n 203
LD ir, r 204
LD IX/Y, (HL) 206
LD IX/Y, (IX/Y + d) 207
LD IX/Y, (Mmn) 209
LD IX/Y, Mmn 208
LD MB, A 215
LD r, (HL) 221
LD r, (IX/Y + d) 224
LD R, A 220
LD r, ir 222
LD r, n 226
LD r, r’ 227
LD rr, (HL) 228
LD rr, (IX/Y + d) 229
LD rr, (Mmn) 231
LD rr, Mmn 230
LD SP, (Mmn) 237
LD SP, HL 234
LD SP, IX/Y 235
LD SP, Mmn 236
LDD 238
LDDR 239
LDI 240
LDIR 241
LEA IX/Y, IX+d 242
LEA IX/Y, IY+d 243
LEA rr, IX+d 244
LEA rr, IY+d 245
legacy code 34, 35
LIFO 10
linear addressing, 16-MB 1, 7
linear addressing, 24-bit 2, 6, 10, 37
Load 202, 203, 204
Load Accumulator 189, 190, 191, 192, 193, 194,
195
Load and Decrement 238
Load and Decrement with Repeat 239
Load and Increment 240
Load and Increment with Repeat 241
Load Effective Address 242, 243, 244, 245
Load Index Register 206, 207, 208, 209
Load Indirect 196, 197, 198, 199, 216, 217, 218,
219, 233
Load Indirect with Offset 210, 211, 212, 214
Load Interrupt Vector 200, 201
Load MBASE 215
Load Refresh Counter 220