Zilog EZ80F916 - Manual (Page 191)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
182
JP (HL)
Jump Indirect
Operation
PC  HL
Description
The Program Counter is loaded with the contents of the multibyte CPU register HL.
Table 59 provides more detailed information on this instruction, particularly when switch-
ing between ADL and Z80 modes.
Condition Bits Affected
None.
Attributes
Table 59. JP (HL) Instruction Detail
ADL Suffix Operation
0 None or
.S The starting Program Counter is {MBASE, PC[15:0]}. Write the 2-byte
value stored in HL[15:0] to PC[15:0]. The ADL mode bit remains cleared
to 0. The ending Program Counter is {MBASE, PC[15:0]} = {MBASE,
HL[15:0]}.
1 None or
.L
The starting Program Counter is PC[23:0]. Write the 3-byte value stored
in HL[23:0] to PC[23:0]. The ADL mode bit remains set to 1. The ending
Program Counter is PC[23:0] = HL[23:0].
0 .L The starting Program Counter is {MBASE, PC[15:0]}. Write the 3-byte
value stored in HL[23:0] to PC[23:0]. Set the ADL mode bit to 1. The
ending Program Counter is PC[23:0] = HL[23:0].
1
.S
The starting Program Counter is PC[23:0]. Write the 2-byte value stored
in HL[15:0] to PC[15:0]. Reset ADL mode bit to 0. The ending Program
Counter is {MBASE, PC[15:0]} = {MBASE, HL[15:0]}.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
JP
(HL) 0/1 3
E9
JP.S
(HL) 1 4
52, E9
JP.L
(HL) 0 4
49, E9