Sbc hl, rr, Operation, Description – Zilog EZ80F916 User Manual
Page 344: Condition bits affected attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
335
SBC HL, rr
Subtract with Carry
Operation
HL HL – rr – C
Description
The rr operand is any of the multibyte CPU registers BC, DE, or HL. The rr operand and
the Carry Flag (C) are subtracted from the contents of the HL register. The result is written
to HL.
Condition Bits Affected
Attributes
kk
identifies either the BC, DE, HL, or SP multibyte register and is assembled into one of
the Opcodes indicated in
S
Set if result is negative; reset otherwise.
Z
Set if result is 0; reset otherwise.
H
Set if borrow from bit 12; reset otherwise.
P/V
Set if overflow; reset otherwise.
N
Set.
C
Set if borrow; reset otherwise.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
SBC
HL,rr
X
2
ED, kk
SBC
.S
HL,rr
1
3
52, ED, kk
SBC
.L
HL,rr
0
3
49, ED, kk