Zilog EZ80F916 - Manual (Page 43)

eZ80
®
CPU
User Manual
UM007715-0415 Mixed-Memory Mode Applications
34
Mixed-Memory Mode Applications
The eZ80 ® CPU contains a control bit flag that affects operation of interrupts, illegal
instruction traps and restart (RST) instructions. The Mixed-ADL (MADL) control bit
must be set to 1 for all applications that run in both Z80 mode and ADL mode. The MADL
control bit can be reset to 0 for all CPU applications that run exclusively in Z80 mode or 
exclusively in ADL mode. Default for the MADL control bit is reset to 0.
No application program can run exclusively in ADL mode, because the default for the
CPU is to begin in Z80 mode. If a single JP.LIL instruction is used at or near the begin-
ning of the source code to permanently change to ADL mode, this program is considered
to operate exclusively in ADL mode.
The purpose of the MADL control bit is to force the CPU to monitor the memory mode
when interrupts, traps or RST instructions occur. If the memory mode does not change,
then the MADL control bit can be reset to 0.
When the MADL control bit is set to 1, the CPU pushes a byte onto the stack that contains
the current memory mode whenever an interrupt, trap, or restart occurs. Even if the mem-
ory mode is not changed by the current interrupt, trap, or restart, the byte containing the
memory mode bit is still pushed onto the stack. A
02h
byte is pushed onto the stack if the
current code is operating in Z80 mode. A
03h
byte is pushed onto the stack if the current
code is operating in ADL mode. The current memory mode is pushed onto the stack prior
to setting the memory mode for the called service routine.
In addition, when the MADL control bit is set to 1 for mixed- memory mode applications,
all interrupts begin in ADL mode.
For applications that run exclusively in a single memory mode (either Z80 or ADL mode),
set the MADL control bit to 1. The CPU always handles interrupts, traps and restarts cor-
rectly if MADL is set to 1.
The MADL control bit is set to 1 by the STMIX instruction. The MADL control bit is
reset to 0 by the RSMIX instruction.
MIXED MEMORY Mode Guidelines
Applications that include legacy code that runs in Z80 mode, and new code that runs in
ADL mode, must follow certain rules to ensure proper operation:
1. Include a STMIX instruction in the device initialization procedure that sets MADL to
1, ensuring that interrupt service routines begin in a consistent memory mode (ADL
mode).
2. End all interrupt service routines with a RETI.L or RETN.L instruction to ensure that
the interrupted code’s memory mode is popped from the SPL stack.