Zilog EZ80F916 - Manual (Page 239)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
230
LD rr, Mmn
Load Register
Operation
rr
 Mmn
Description
The rr operand is any of the multibyte CPU registers BC, DE, or HL. The immediate
operand, Mmn, is written to the multibyte rr register.
Condition Bits Affected
None.
Attributes
kk
identifies the BC, DE, HL, or SPI register and is assembled into one of the opcodes
indicated in Table 71 .
Mnemonic Operand ADL Mode Cycle Opcode (hex)
LD ss
,mn 0 3
kk, nn, mm
LD ss
,Mmn 1 4
kk, nn, mm, MM
LD.LIL ss
,Mmn 0 5
5B, kk, nn, mm, MM
LD.SIS ss
,mn 1 4
40, kk, nn, mm
Table 71. Register and kk Opcodes for LD rr, Mmn Instruction (hex)
Register kk
BC
01
DE
11
HL
21