Pea iy+d, Operation, Description – Zilog EZ80F916 User Manual
Page 285: Condition bits affected, Attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
276
PEA IY+d
Push Effective Address
Operation
if ADL mode{
( SPL – 1) IYd[23:16]
(SPL – 2) IYd[15:8]
(SPL – 3) IYd[7:0]
SPL SPL – 3
}
else Z80 mode {
(SPS – 1) IYd[15:8]
(SPS – 2) IYd[7:0]
SPS SPS – 2
}
where IYd indicates the sum of the contents of the register IY and the two’s-complement
displacement d
.
Description
In ADL mode, the 24-bit sum of the contents of IY and the two’s-complement displace-
ment d is pushed onto the stack at SPL. The stack pointer, SPL, decrements by 3. The
most significant byte (MSB) is pushed onto the stack first.
In Z80 mode, the 16-bit sum of the contents of IY and the two’s-complement displacement
d
is pushed onto the stack at SPS. The stack pointer, SPS, decrements by 2. The most sig-
nificant byte (MSB) is pushed onto the stack first.
Condition Bits Affected
None.
Attributes
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
PEA
IY+d
0/1
5/6
ED, 66, dd
PEA.S
IY+d
1
6
52, ED, 66, dd
PEA.L
IY+d
0
7
49, ED, 66, dd