Otimr, Operation, Description – Zilog EZ80F916 User Manual
Page 274: Condition bits affected attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
265
OTIMR
Output to I/O and Increment
Operation
repeat {
({UU, 00h, C}) (HL)
B B – 1
C C+1
HL HL+1
} while B 0
Description
The CPU loads the contents of the memory location specified by the multibyte HL register
into CPU memory. The CPU next outputs this byte to the I/O address specified by the C
register with the High byte of the address, ADDR[15:8], forced to 0. The upper byte of the
address bus, ADDR[23:16] is undefined for I/O addresses. The B register decrements. The
C and HL registers increment. The instruction repeats until the B register equals 0.
Condition Bits Affected
Attributes
S
Undefined.
Z
Set if B – 1 = 0; reset otherwise.
H
Undefined.
P/V
Undefined.
N
Set if msb of data is logical 1; reset otherwise.
C
Undefined.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
OTIMR
—
X
2
+
3
*
B
ED, 93
OTIMR.S
—
1
3
+
3
*
B
52, ED, 93
OTIMR.L
—
0
3
+
3
*
B
49, ED, 93