Inc r, Operation, Description – Zilog EZ80F916 User Manual
Page 168: Condition bits affected attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
159
INC r
Increment
Operation
r
r+1
Description
The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. The CPU incre-
ments the contents of the specified register r by 1.
Condition Bits Affected
Attributes
jj
identifies the A, B, C, D, E, H, or L register and is assembled into one of the opcodes
.
S
Set if result is negative; reset otherwise.
Z
Set if result is 0; reset otherwise.
H
Set if carry from bit 3.
P/V
Set if operand was 7Fh before operation; reset otherwise.
N
Reset.
C
Not affected.
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
INC
r
X
1
jj
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