Ld (hl), rr, Operation, Description – Zilog EZ80F916 User Manual
Page 208: Condition bits affected, Attributes
eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
199
LD (HL), rr
Load Indirect
Operation
(HL) rr
Description
The rr operand is any of the multibyte registers BC, DE, or HL. The CPU writes the con-
tents of the multibyte register rr to the memory location specified by the contents of the
multibyte HL register.
Condition Bits Affected
None.
Attributes
Mnemonic
Operand
ADL Mode
Cycle
Opcode (hex)
LD
(HL),BC
0/1
4/5
ED, 0F
LD.S
(HL),BC
1
5
52, ED, 0F
LD.L
(HL),BC
0
6
49, ED, 0F
LD
(HL),DE
0/1
4/5
ED, 1F,
LD.S
(HL),DE
1
5
52, ED, 1F
LD.L
(HL),DE
0
6
49, ED, 1F
LD
(HL),HL
0/1
4/5
ED, 2F
LD.S
(HL),HL
1
5
52, ED, 2F
LD.L
(HL),HL
0
6
49, ED, 2F
This manual is related to the following products: