Ld (mmn), sp, Operation, Description – Zilog EZ80F916 User Manual
Page 228: Condition bits affected, Attributes

eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
219
LD (Mmn), SP
Load Indirect
Operation
(Mmn)
SP
Description
The CPU stores the contents of the multibyte Stack Pointer Register SP in the memory
location specified by Mmn. In ADL mode, if SP is chosen, Stack Pointer Long (SPL) is
the source. In Z80 mode, if SP is chosen, Stack Pointer Short (SPS) is the source.
Condition Bits Affected
None.
Attributes
Zilog recommends against using the .SIL and .LIS suffixes with this instruction. The .SIL
instruction fetches a 24-bit value, Mmn. However, this instruction ignores the upper byte
and uses address {MBASE, mm, nn} instead. The .LIS instruction fetches a 16-bit value,
mn. However, the .LIS instruction does not use the MBASE value. Instead, it uses address
{00, mm, nn}.
Mnemonic Operand
ADL
Mode
Cycle
Opcode (hex)
LD
(mn)
,SP
0
6
ED, 73, nn, mm
LD
(Mmn)
,SP 1
8
ED, 73, nn, mm, MM
LD.SIS
(mn)
,SP
1
7
40, ED, 73, nn, mm
LD.LIL
(Mmn)
,SP 0
9
5B, ED, 73, nn, mm, MM
Note: