Zilog EZ80F916 - Manual (Page 238)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
229
LD rr, (IX/Y+d)
Load Register
Operation
rr
 (IX/Y+d)
Description
The rr operand is any of the multibyte CPU registers BC, DE, or HL. The CPU writes the
contents of the memory location, specified by the contents of the IX or IY register offset
by the two’s-complement displacement d, to the multibyte rr register.
Condition Bits Affected
None.
Attributes
Mnemonic Operand ADL Mode Cycle Opcode (hex)
LD
BC,(IX+d) 0/1 5/6
DD, 07, dd
LD.S
BC,(IX+d) 1 6
52, DD, 07, dd
LD.L
BC,(IX+d) 0 7
49, DD, 07, dd
LD
DE,(IX+d) 0/1 5/6
DD, 17, dd
LD.S
DE,(IX+d) 1 6
52, DD, 17, dd
LD.L
DE,(IX+d) 0 7
49, DD, 17, dd
LD
HL,(IX+d) 0/1 5/6
DD, 27, dd
LD.S
HL,(IX+d) 1 6
52, DD, 27, dd
LD.L
HL,(IX+d) 0 7
49, DD, 27, dd
LD
BC,(IY+d) 0/1 5/6
FD, 07, dd
LD.S
BC,(IY+d) 1 6
52, FD, 07, dd
LD.L
BC,(IY+d) 0 7
49, FD, 07, dd
LD
DE,(IY+d) 0/1 4/5
FD, 17, dd
LD.S
DE,(IY+d) 1 5
52, FD, 17, dd
LD.L
DE,(IY+d) 0 6
49, FD, 17, dd
LD
HL,(IY+d) 0/1 4/5
FD, 27, dd
LD.S
HL,(IY+d) 1 5
52, FD, 27, dd
LD.L
HL,(IY+d) 0 6
49, FD, 27, dd