Zilog EZ80F916 - Manual (Page 249)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
240
LDI
Load and Increment
Operation
(DE)  (HL)
BC  BC – 1
DE  DE+1
HL  HL+1
Description
The CPU writes the contents of the memory location with address contained in the multi-
byte register HL to the memory location with address contained in the multibyte register
DE. The BC register decrements. The DE and HL registers increment.
Condition Bits Affected
Attributes
S
Not affected.
Z
Not affected.
H
Reset.
P/V
Reset if BC 1 = 0; set otherwise.
N
Reset.
C
Not affected.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
LDI
— X 5
ED, A0
LDI.S
— 1 6
52, ED, A0
LDI.L
— 0 6
49, ED, A0