Zilog EZ80F916 - Manual (Page 51)

eZ80
®
CPU
User Manual
UM007715-0415 Interrupts
42
Table 24. Interrupt Mode 2 Operation
Memory Mode
ADL

Bit
MADL

Bit Operation
Z80 Mode 0 0 Read the LSB of the interrupt vector placed on the data bus,
D[7:0], by the interrupting peripheral.
• IEF1  0
• IEF2  0
• The starting Program Counter is effectively {MBASE,
PC[15:0]}.
• Push the 2-byte return address PC[15:0] onto the
({MBASE,SPS}) stack.
• The ADL mode bit remains cleared to 0.
• The interrupt vector address is located at { MBASE,
I[7:0], D[7:0] }.
• PC[15:0]  ( { MBASE, I[7:0], D[7:0] } ).
• The ending Program Counter is effectively {MBASE,
PC[15:0]}
• The interrupt service routine must end with RETI.
ADL Mode 1 0 Read the LSB of the interrupt vector placed on the data bus,
D[7:0], by the interrupting peripheral.
• IEF1  0
• IEF2  0
• The starting Program Counter is PC[23:0].
• Push the 3-byte return address, PC[23:0], onto the SPL
stack.
• The ADL mode bit remains set to 1.
• The interrupt vector address is located at { I[15:0], D[7:0]
}.
• PC[23:0]  ( {I[15:0], D[7:0] } ).
• The ending Program Counter is { PC[23:0] }.
• The interrupt service routine must end with RETI.