Zilog EZ80F916 - Manual (Page 357)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
348
SRA (HL)
Shift Right Arithmetic
Operation
Description
The (HL) operand is an 8-bit value at the memory location specified by the contents of the
multibyte register (HL). The CPU manipulates the contents of this memory location, (HL),
by shifting them right one bit position. The CPU next copies the contents of bit 0 into the
Carry Flag and leaves the previous contents of bit 7 unchanged.
Condition Bits Affected
Attributes
S
Set if result is negative; reset otherwise.
Z
Set if result is 0; reset otherwise.
H
Reset.
P/V
Set if parity is even; reset otherwise.
N
Reset.
C
Data from bit 0 of the source.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
SRA
(HL) X 5
CB, 2E
SRA.S
(HL) 1 6
52, CB, 2E
SRA.L
(HL) 0 6
49, CB, 2E
C 7 0
(HL)