Adc a, ir, Operation, Description – Zilog EZ80F916 User Manual
Page 89: Condition bits affected attributes

eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
80
ADC A, ir
ADD with Carry
Operation
A A+ir+C
Description
The ir operand is any of the 8-bit registers IXH, IXL, IYH, or IYL. The ir operand and the
Carry Flag (C) are added to the contents of the accumulator, A. The result is stored in the
accumulator.
Condition Bits Affected
Attributes
S
Set if result is negative; reset otherwise.
Z
Set if result is 0; reset otherwise.
H
Set if carry from bit 3; reset otherwise.
P/V
Set if overflow; reset otherwise.
N
Reset.
C
Set if carry from bit 7; reset otherwise.
Mnemonic
Operand
ADL Mode
Cycle
Opcode (hex)
ADC
A,IXH
X
2
DD, 8C
ADC
A,IXL
X
2
DD, 8D
ADC
A,IYH
X
2
FD, 8C
ADC
A,IYL
X
2
FD, 8D
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