Zilog EZ80F916 - Manual (Page 184)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
175
INIM
Input from I/O and Increment
Operation
(HL)  ({UU, 00h, C})
B  B – 1
C  C+1
HL  HL+1
Description
The CPU places the contents of register C onto the lower byte of the address bus,
ADDR[7:0], and places a 0 onto the High byte of the address bus, ADDR[15:8]. The
upper byte of the address bus, ADDR[23:16] is undefined for I/O addresses. The CPU
reads the byte located at I/O address {UU,
00h
, C} into CPU memory. The CPU next
places the contents of HL onto the address bus and writes the byte to the memory address
specified by the HL register. The B register decrements. The C and HL registers incre-
ment. The Z Flag is set to 1 if the B register decrements to 0.
Condition Bits Affected
Attributes
S
Undefined.
Z
Set if B – 1 = 0; reset otherwise.
H
Undefined.
P/V
Undefined.
N
Set if msb of data is a logical 1; reset otherwise.
C
Undefined.
Mnemonic Operand ADL Mode Cycle Opcode (hex)
INIM
— X 5
ED, 82
INIM.S
— 1 6
52, ED, 82
INIM.L
— 0 6
49, ED, 82