Zilog EZ80F916 User Manual
Page 397
eZ80
®
CPU
User Manual
UM007715-0415
Glossary
388
IPR.
Interrupt Priority Register.
IRQ.
Interrupt Request.
ISR.
See Interrupt Service Routine.
IVEDCT bus.
An internal 8-bit bus used by on-chip peripherals for passing an interrupt vector address byte
to the eZ80
®
CPU.
JP.
Jump; a program control instruction.
JP cc.
Conditional Jump; a program control instruction.
JR.
Jump Relative; a program control instruction.
JR cc.
Conditional Jump Relative; a program control instruction.
Latch.
A hardware service that senses information and holds it until reset.
LD.
Load; an arithmetic instruction.
LDD (LDDR).
Load and Decrement (with Repeat); a block transfer instruction.
LDI (LDIR).
Load and Increment (with Repeat); a block transfer instruction.
LEA.
Load Effective Address; a load instruction.
little-endian.
A computer architecture in which, within a given 16- or 32-bit word, bytes at lower
addresses bear lower significance (the word is stored “little-end-first”). The PDP-11 and VAX families of
computers and a lot of communications and networking hardware are little-endian.
low-pass filter.
A filter network that passes all frequencies below a specified frequency with little or no
loss, but strongly attenuates higher frequencies.
lsb.
least significant bit.
LSB.
Least Significant Byte.
MAC.
MAC An acronym for Media Access Control, the method a computer uses to transmit or receive
data across a LAN.
MADL.
See Mixed-ADL mode.
Main register set.
One of two banks of working registers in the eZ80
®
CPU. The main register set
contains the 8-bit accumulator register (A) and six 8-bit working registers (B, C, D, E, H, and L). See
Alternate register set.
Maskable Interrupt.
Maskable interrupts can be enabled and disabled. If enabled, the eZ80
®
CPU will
respond to a maskable interrupt service request from an external device or on-chip peripheral. If disabled,
the eZ80
®
CPU will not respond to an maskable interrupt service request from an external device or on-
chip peripheral. A maskable interrupt can be disabled by the programmer. See nonmaskable interrupt.
MBASE.
Z80 Memory Mode Base Address Register. The 8-bit MBASE register determines the page of
memory currently employed when operating in Z80 mode. The MBASE register is only used during Z80
mode. However, the MBASE register can only be altered from within ADL mode.
MIE.
Master Interrupt Enable.
Mixed-ADL mode (MADL).
The MADL control bit is used to indicate whether or not a program contains
code that runs in both ADL and Z80 MEMORY modes. Also Mixed-Memory Mode Flag.
MLT.
Multiply; an arithmetic instruction.
msb.
most significant bit.