Zilog EZ80F916 - Manual (Page 351)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
342
SET b, r
Set Bit
Operation
r
[b]  1
Description
The r operand is any of the 8-bit CPU registers A, B, C, D, E, H, or L. Bit b of the speci-
fied register is set to 1.
Condition Bits Affected
None.
Attributes
jj
= binary code
11 bbb rrr
and
kk
= binary code
11 bbb 110
; where
rrr
identifies
the A, B, C, D, E, H, or L register and
bbb
identifies the bit tested and assembled into the
object code, as indicated in Table 98 .
Mnemonic Operand ADL Mode Cycle Opcode (hex)
SET b
,r X 2
CB, jj
Table 98. bbb , Register, and rrr Opcodes for SET b, r Instruction (hex)
Bit

Tested bbb Register rrr
0
000
A
111
1
001
B
000
2
010
C
001
3
011
D
010
4
100
E
011
5
101
H
100
6
110
L
101
7
111