Zilog EZ80F916 User Manual

Page 28

eZ80

CPU

User Manual

UM007715-0415

Memory Mode Switching

Each of the four suffixes .SIS, .SIL, .LIS, and .LIL is composed of 2 parts that define the

operation in the control block and the data block within the CPU (see

). The first part of the suffix, either Short (.S) or Long (.L), directs operations

within the data block of the CPU. .S and .L control whether the overall operation of the

instruction and the internal registers should use 16 or 24 bits. The .S and .L portions of the

suffix also indicate if MBASE is used to define the 24-bit address. The last part of the suf-

fix, either .IS or .IL, directs the control block within the CPU. The Instruction Stream

Short and Instruction Stream Long suffixes, .IS and .IL, control whether a multibyte

immediate data or address value fetched during instruction execution is 2 or 3 bytes long

(for example, a LD HL, Mmn instruction versus a LD HL, mn instruction). The CPU

must know whether to fetch 3 bytes (Mmn) or 2 bytes (mn) of data. The .IS and .IL por-

tions of the suffix tell the CPU the length of the instruction. If the length of the instruction

is unambiguous, the .IS and .IL suffixes yield no effect.
Table 10. Opcode Suffix Description

Full Suffix

Suffix
Components Description

.SIS

The CPU data block operates in Z80 mode using 16-bit

registers. All addresses use MBASE.

.IS

The CPU control block operates in Z80 mode. For

instructions with an ambiguous number of bytes, the .IS

suffix indicates that only 2 bytes of immediate data or

address must be fetched.

.SIL

The CPU data block operates in Z80 mode using 16-bit

registers. All addresses use MBASE.

.IL

The CPU control block operates in ADL mode. For

instructions with an ambiguous number of bytes, the .IL

suffix indicates that 3 bytes of immediate data or address

must be fetched.

.LIS

The CPU data block operates in ADL mode using 24-bit

registers. Addresses do not use MBASE.

.IS