Zilog EZ80F916 - Manual (Page 73)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
64
INDRX
repeat {
(HL)  ({00h, DE[15:0]})
BC  BC – 1
HL  HL – 1
} while BC  0
ED CA
— 1 — — * —
INI
(HL)  ({00h, BC[15:0]})
B  B – 1
HL  HL+1
ED A2
— * — — * —
INI2
(HL)  ({00h, BC[15:0]})
B  B – 1
C  C+1
HL  HL+1
ED 84
— * — — * —
INI2R
repeat {
(HL)  ({00h, DE[15:0]})
BC  BC – 1
DE  DE+1
HL  HL+1
} while BC  0
ED 94
— 1 — — * —
INIM
(HL)  ({0000h, C})
B  B – 1
C  C+1
HL  HL+1
ED 82
X * X X * X
Table 37. Instruction Summary (Continued)
Instruction and Operation
Address Mode
Opcode(s)
(Hex)
Flags Affected
Dest Source S Z H P/V N C
Note: *This flag value is a function of the result of the affected operation.
— = No Change.
0 = Set to 0.
1 = Set to 1.
V = Set to 1 if overflow occurs.
X = Undetermined.
P = Set to the parity of the result (0 if odd parity, 1 if even parity).
IEF2 = The value of Interrupt Enable Flag 2.