Zilog EZ80F916 - Manual (Page 170)

eZ80
®
CPU
User Manual
UM007715-0415 CPU Instruction Set
161
INC rr
Increment
Operation
rr
 rr+1
Description
The rr operand is any of the multibyte CPU registers BC, DE, or HL. The CPU incre-
ments the contents of the specified register by 1. In Z80 mode, or when the .S suffix is
employed, rr[23:16] 
00h
.
Condition Bits Affected
None.
Attributes
kk
identifies the BC, DE, or HL register and is assembled into one of the opcodes indi-
cated in Table 57 .
Mnemonic Operand ADL Mode Cycle Opcode (hex)
INC rr
X 1
kk
INC.S rr
1 2
52, kk
INC
.L
rr
0 2
49, kk
Table 57. Register and kk Opcodes for INC rr Instruction (hex)
Register kk
BC
03
DE
13
HL
23