Ld ix/y, (ix/y+d), Operation, Description – Zilog EZ80F916 User Manual
Page 216: Condition bits affected, Attributes

eZ80
®
CPU
User Manual
UM007715-0415
CPU Instruction Set
207
LD IX/Y, (IX/Y+d)
Load Index Register
Operation
IX/Y
(IX/Y+d)
Description
The CPU writes the contents of the memory location, specified by the contents of the IX
or IY register offset by the two’s-complement displacement d, to the multibyte Index Reg-
ister, IX or IY.
Condition Bits Affected
None.
Attributes
Mnemonic Operand
ADL Mode Cycle
Opcode (hex)
LD
IX,(IX+d)
0/1
5/6
DD, 37, dd
LD.S
IX,(IX+d)
1
6
52, DD, 37, dd
LD.L
IX,(IX+d)
0
7
49, DD, 37, dd
LD
IY,(IX+d)
0/1
5/6
DD, 31, dd
LD.S
IY,(IX+d)
1
6
52, DD, 31, dd
LD.L
IY,(IX+d)
0
7
49, DD, 31, dd
LD
IX,(IY+d)
0/1
5/6
FD, 31, dd
LD.S
IX,(IY+d)
1
6
52, FD, 31, dd
LD.L
IX,(IY+d)
0
7
49, FD, 31, dd
LD
IY,(IY+d)
0/1
5/6
FD, 37, dd
LD.S
IY,(IY+d)
1
6
52, FD, 37, dd
LD.L
IY,(IY+d)
0
7
49, FD, 37, dd