beautypg.com

7 external interrupt ena, Maxq7667 user’s guide – Maxim Integrated MAXQ7667 User Manual

Page 84

background image

5-9

___________________________________________________________________________________________________________

MAXQ7667 User’s Guide

5.2.7 External Interrupt Enable Register (Port 0) (EIE0)

Register Description:

External Interrupt Enable Register (Port 0)

Register Name:

EIE0

Register Address:

Module 00h, Index 0Bh

Bits 15 to 8: Reserved. Read returns 0, write ignored.

Bit 7: Enable External Interrupt 7 (EX7). Setting this bit to 1 enables external interrupt 7. Clearing this bit to 0 disables the
interrupt function.

Bit 6: Enable External Interrupt 6 (EX6). Setting this bit to 1 enables external interrupt 6. Clearing this bit to 0 disables the
interrupt function.

Bit 5: Enable External Interrupt 5 (EX5). Setting this bit to 1 enables external interrupt 5. Clearing this bit to 0 disables the
interrupt function.

Bit 4: Enable External Interrupt 4 (EX4). Setting this bit to 1 enables external interrupt 4. Clearing this bit to 0 disables the
interrupt function.

Bit 3: Enable External Interrupt 3 (EX3). Setting this bit to 1 enables external interrupt 3. Clearing this bit to 0 disables the
interrupt function.

Bit 2: Enable External Interrupt 2 (EX2). Setting this bit to 1 enables external interrupt 2. Clearing this bit to 0 disables the
interrupt function.

Bit 1: Enable External Interrupt 1 (EX1). Setting this bit to 1 enables external interrupt 1. Clearing this bit to 0 disables the
interrupt function.

Bit 0: Enable External Interrupt 0 (EX0). Setting this bit to 1 enables external interrupt 0. Clearing this bit to 0 disables the
interrupt function.

r = read, w = write

Note: The reset value for this register is dependent on the logical states of the pins.

Bit #

15

14

13

12

11

10

9

8

Name

Reset

0

0

0

0

0

0

0

0

Access

r

r

r

r

r

r

r

r

Bit #

7

6

5

4

3

2

1

0

Name

EX7

EX6

EX5

EX4

EX3

EX2

EX1

EX0

Reset

0

0

0

0

0

0

0

0

Access

rw

rw

rw

rw

rw

rw

rw

rw