3 sar adc registers, 1 sar adc control regis, 3 sar adc registers -5 – Maxim Integrated MAXQ7667 User Manual
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MAXQ7667 User’s Guide
14.3 SAR ADC Registers
14.3.1 SAR ADC Control Register (SARC)
Register Description:
SAR ADC Control Register
Register Name:
SARC
Register Address:
Module 05h, Index 02h
Bits 15 to 12: Reserved. Read returns 0.
Bits 11 to 9: Analog Input Mux Control (SARMX[2:0])
For SARDIF = 0:
000 selects AIN0 vs. AGND
001 selects AIN1 vs. AGND
010 selects AIN2 vs. AGND
011 selects AIN3 vs. AGND
100 selects AIN4 vs. AGND
101 measures REF vs. AGND; AVDD is used as the reference by setting SARRSEL (see Section 14.5.11)
For SARDIF = 1:
000 selects AIN0 vs. AIN1
001 selects AIN2 vs. AIN3
Bit 8: SAR ADC Differential Input Select (SARDIF). When set to 1, this bit selects differential measurements. When set to 0, this bit
selects single-ended measurements relative to AGND.
Bit 7: SAR ADC Bipolar Input Select (SARBIP). When set to 1, this bit selects bipolar mode with differential analog input range of
-V
REF
/2 to +V
REF
/2. When set to 0. this bit selects unipolar mode with differential analog input range of 0 to V
REF
.
Bit 6: Dual-Edge Conversion Start Mode Select (SARDUL). This bit determines the SAR ADC’s acquisition timing. When 1, the ADC is
operated in dual-edge mode. The rising edge of the ADC conversion control source (specified by SARS) causes the ADC to power-up
and begin acquisition, and the falling edge causes the ADC to sample and perform a conversion. When 0, the ADC is operated in single-
edge mode. The rising edge of the ADC conversion control source causes the ADC to power-up, acquire, and convert automatically.
Bit 5: SAR ADC Reference Select (SARRSEL). When set to 1, this bit selects AVDD as reference. When set to 0, this bit selects the
REF pin voltage as reference.
Bit 4: SAR ADC Auto Shutdown Enable (SARASD). When 1, the SAR ADC shuts down automatically after a conversion is complete.
When 0, the SAR ADC is powered up as long as SARE is 1.
Note: If SAR ADC is in continuous conversion (i.e., SARS = 110), SARASD
is ignored.
Bit #
15
14
13
12
11
10
9
8
Name
—
—
—
—
SARMX2
SARMX1
SARMX0
SARDIF
Reset
0
0
0
0
0
0
0
0
Access
r
r
r
r
rw
rw
rw
rw
Bit #
7
6
5
4
3
2
1
0
Name
SARBIP
SARDUL
SARRSEL
SARASD
SARBY
SARS2
SARS1
SARS0
Reset
0
0
0
0
0
1
1
1
Access
rw
rw
rw
rw
rw
rw
rw
rw
r = read, w = write
Note: SARC is cleared to 0007h on all forms of reset.