Maxim Integrated MAXQ7667 - Manual (Page 152)

8.4.5.3 LIN Slave Polling for Receive Complete Example
One method to accomplish this is to use the LIN interrupts to monitor the LIN state in the ISVEC register similar to what the master does.
Using the LIN interrupt handler, ISVEC state 2 indicates when the protected identifier has been successfully received in slave mode.
• In the interrupt handler a flag (e.g., RX_OK = 1) is set for state 2.
• Wait until RX_OK = 1 before proceeding.
This method is inefficient because the processor must wait for the receive data to be complete instead of doing other tasks.
8.4.5.4 LIN Slave Setup to Transmit Data from Slave Example
Once the break/sync has been received with a valid protected identifier, the slave can respond to the master by sending data and the
checksum. To send the master data, the frame length and the RTN bit must be set and the data must be loaded to SBUF. (Note that
changes to CNT1 should happen with one single write to the register.) The following example sends one data byte to the master. Note
that the number of bytes of data transmitted is one greater than what is sent in CNT1. The checksum is automatically calculated and
sent by the LIN controller, and requires no software intervention from the MAXQ processor.
• Set CNT1 to transmit 1 byte (CNT1 = 0x00).
• Load transmit data into SBUF.
8.4.5.5 LIN Slave Setup to Transmit Multiple Bytes from Slave Example
If more than one byte is to be sent, the FIFO can be enabled to send up to eight bytes (see Section 8.4.8: LIN Transmit and Receive
FIFO) or the SBUF can be written successively. If using the SBUF to write successively, the MAXQ processor must wait until the previ-
ous SBUF contents have been shifted out over the LIN bus. One method to wait is to detect if the LIN state machine is busy by moni-
toring the BUSY bit in the STA0 register as shown in the following example. The example demonstrates the monitoring of the BUSY bit
between write to SBUF.
• Load transmit data into SBUF.
• Wait until STA0 busy bit is no longer set (STA0 = 1).
• Load transmit data into SBUF.
• Wait until STA0 busy bit is no longer set (STA0 = 1).
8.4.6 Receive Filter
The LIN receive path shown in Figure 8-3 contains a noise filter to reject spurious bus noise. The filter is programmable to reject
between two and six system clocks. To enable the receive filter and set the filter parameters, the receive filter prescalar mode (FP[1:0])
bits in CNT0 are used.
8.4.7 Identifier Boundary Register (IDFB)
The Identifier Boundary (IDFB) register follows the receive filter (see Figure 8-3). IDFB is used to filter the incoming message identifi-
er. The master transmits the identifier in the range of 0x00–0x3F. The slave can set the lower limit and the upper limit of identifiers that
the slave recognizes. By setting these limits, the slave can reply to a range of valid identifiers or to a single identifier. If the identifier
transmitted by the master is not within the range of valid identifiers set on the slave, the message is ignored by the slave. IDFB has a
power-on reset value of 0x3F00 that accepts all identifiers.
8.4.8 LIN Transmit and Receive FIFO
To reduce the load on the processor, both transmit and receive paths have 8-byte FIFOs. The transmit and receive FIFOs are both
enabled or disabled with the FIFO enable (FEN) bit in FCON. The FIFOs can also be cleared independently with the flush receive FIFO
(FRF) and the flush transmit FIFO (FTF) bits. Both the transmit and receive FIFO have independent thresholds that are programmable
to signal the processor when the receive FIFO is almost full or the transmit FIFO is almost empty. The receive FIFO threshold (RXFT)
bits set the number of bytes that are in the receive FIFO when the almost full flag causes an interrupt. Conversely, the transmit FIFO
threshold (TXFT) bits set the number of bytes that are in the transmit FIFO when the almost empty flag causes an interrupt. The trans-
mit and receive FIFO status can be monitored by reading FSTAT. The following steps can be used to enable the FIFO.
• Set FEN bit (FCON.0) to 1 to enable LIN FIFO.
• Set FRF bit (FCON.6) to 1 to reset receive FIFO pointer and flags.
• Set FTF bit (FCON.7) to 1 to reset the transmit FIFO pointer and flags.
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MAXQ7667 User’s Guide