Maxim Integrated MAXQ7667 - Manual (Page 144)

8.3.12 Control Register 2 (UART) (CNT2)
Register Description: Control Register 2
Register Name: CNT2
Register Address: Module 03h, Index 15h
Bits 7 to 5: Reserved. Read returns 0.
Bit 4: Data Mismatch Disable (DMIS). When this bit is set to 1 data mismatch detection is disabled (ERRR.5).
Bit 3: Power Management (PM). This bit controls the behavior of interrupt generation when the peripheral is in the low-power sleep
mode. If this bit is set to 1, the peripheral issues an interrupt as soon as any bus activity is detected in sleep mode. If this bit is cleared
to 0, the peripheral does not issue any interrupts until a wake-up request is detected.
Bit 2: Header Only (HDO). When this bit is set to 1, the peripheral receives a LIN header only and ignores all data in the frame. If this
bit is set to 1 before a LIN header has been received, it automatically is cleared to 0 by the peripheral when a header is received. If
this bit is set to 1 by the host after the peripheral has been processed a valid header, the receive buffer is emptied and the peripher-
al returns to the dominant state.
Bit 1: Force Break/Sync (FBS). If this bit is set to 1 while a peripheral is configured in LIN master mode, the peripheral issues a
break/sync sequence on the LIN bus. The host must write the identifier for the frame into the transmit buffer. Parity bits for the trans-
mitted identifier are computed automatically.
Bit 0: Break Threshold (BTH). This bit is used to select between a 10-bit (BTH = 0) or 11-bit (BTH = 1) detection threshold for a break
symbol on the LIN bus.
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MAXQ7667 User’s Guide
r = read, w = write
Note: CNT2 is cleared to 00h on all forms of reset.
Bit # 7 6 5 4 3 2 1 0
Name — — — DMIS PM HDO FBS BTH
Reset 0 0 0 0 0 0 0 0
Access r r rw rw rw rw rw rw