Maxim Integrated MAXQ7667 - Manual (Page 216)

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MAXQ7667 User’s Guide
12.3.9 Debug Mode Special Considerations
The following are special considerations when using debug mode.
The debug engine cannot be operated reliably when the CPU is configured in the power management mode (divide-by-256 system
clock mode). To allow for proper execution of debug mode commands when invoked during PMM, the switchback enable (SWB) bit
should be configured to logic 1. With SWB = 1, entering active debug mode (whether by breakpoint match or issuance of the debug
command) forces a switchback to the divide-by-1 system clock mode and allows the debug engine to function correctly. This allows
user code to configure breakpoints that occur inside PMM, thus providing reliable use of debug commands. However, it does not allow
a good means for re-entering PMM.
• Special caution should be exercised when using the write-register command on register bits that globally affect system operation
(e.g., IGE, STOP). If the write-register command is used to invoke STOP mode (setting STOP = 1), the RST pin can be asserted
to reset the debug engine and return to the background mode of operation.
• Single stepping (trace) through any IGE bit change operation results in the debug engine overriding the bit change since it retains
the IGE bit setting captured when active debug mode was entered.
• Single stepping (trace) into an operation that sets STOP = 1 when IGE = 1 effectively allows enabled interrupts normally capable
of causing exit from STOP mode to do so.
• Single stepping (trace) through any memory read instruction that reads from the utility ROM (such as "move Acc," @DP[0] with
DP[0] set to 8000h) causes the memory read to return an incorrect value.
• Single stepping (trace) cannot be used when executing code from the utility ROM.
• Data memory allocation is important during system development if in-circuit debug is planned. The top 32-byte memory location
can be used by the debug service routine during debug mode. The data contents in these locations can be altered and cannot
be recovered.
• One available stack location is needed for debug mode. If the stack is full when entering debug mode, the oldest data in the stack
will be overwritten.
• The crystal warmup counter is the only counter not disabled when active debug mode is entered. If the crystal warmup counter
completes while in active debug mode, a glitchless switch will be made to selected clock source, which was being counted. It is
important the user recognize that this action will occur as the TAP clock should be run no faster than 1/8th the system clock fre-
quency.
• Any signal sampling that relies upon the internal system clock (e.g., counter inputs) can be unreliable since the system clock is
turned off inside active debug mode between debug mode commands.