Maxim Integrated MAXQ7667 - Manual (Page 203)

12-5 __________________________________________________________________________________________________________
MAXQ7667 User’s Guide
12.2.2 In-Circuit Debug Temporary 1 Register (ICDT1)
The ICDT1 register is read/write accessible by the CPU only in background mode or debug mode. This register is intended for use by
the utility ROM routines as temporary storage to save registers that might otherwise have to be placed in the stack. This register is
cleared after a power-on reset or by a test-logic-reset TAP state.
Register Description: In-Circuit Debug Temporary 1 Register
Register Name: ICDT1
Register Address: Module 02h, Index 19h
Bits 15 to 0: In-Circuit Debug Temporary 1 Register Bits 15:0 (ICDT1[15:0])
12.2.3 In-Circuit Debug Control Register (ICDC)
The ICDC register is read/write accessible by the debug engine and is read only by the CPU. This register is cleared after a power-on
reset or by a test-logic-reset TAP state.
Register Description: In-Circuit Debug Control Register
Register Name: ICDC
Register Address: Module 02h, Index 1Ah
Bit 7: Debug Mode Enable (DME). When this bit is cleared to 0, background mode commands can be executed but breakpoints are
disabled. When this bit is set to 1, breakpoints are enabled while background mode commands can still be entered. This bit can only
be set or cleared from debug mode. This bit has no meaning for the ROM code.
Bits 6 and 4: Reserved. Read 0, write ignored.
s = special (read/write access only in background or debug mode)
Bit # 15 14 13 12 11 10 9 8
Name ICDT115 ICDT114 ICDT113 ICDT112 ICDT111 ICDT110 ICDT19 ICDT18
Reset 0 0 0 0 0 0 0 0
Access s s s s s s s s
Bit # 7 6 5 4 3 2 1 0
Name ICDT17 ICDT16 ICDT15 ICDT14 ICDT13 ICDT12 ICDT11 ICDT10
Reset 0 0 0 0 0 0 0 0
Access s s s s s s s s
r = read, s = special (write only by debug engine)
Bit # 7 6 5 4 3 2 1 0
Name DME — REGE — CMD3 CMD2 CMD1 CMD0
Reset 0 0 0 0 0 0 0 0
Access rs r rs r rs rs rs rs