beautypg.com

2 maxq7667 uart modes, 1 uart mode 0, 2 uart mode 1 – Maxim Integrated MAXQ7667 User Manual

Page 155: 2 maxq7667 uart modes -25, 1 uart mode 0 -25, 2 uart mode 1 -25, Maxq7667 user’s guide

background image

8.5.2 MAXQ7667 UART Modes

8.5.2.1 UART Mode 0

This mode is used to communicate in synchronous, half-duplex format with devices that accept the MAXQ7667 microcontroller as a

master. Figure 8-7 shows a functional diagram and basic timing of this mode. As can be seen, there is one bidirectional data line (Rx)

and one shift clock line (Tx) used for communication. Mode 0 requires that the MAXQ7667 be the master since it generates the serial

shift clock for data transfers that occur in either direction.

The Rx signal is used for both transmission and reception. Data bits enter and exit least significant bit first. The Tx pin provides the

shift clock. The baud rate is equal to the shift clock frequency. When not using power management mode, the baud rate in mode 0 is

equivalent to the system clock divided by either 12 or 4, as selected by SM2 bit in the SCON register.

The UART begins transmitting when a write is performed on SBUF. The internal shift register then begins to shift data out. The clock is

activated and transfers data until the 8-bit value is complete. Data is presented one clock prior to the falling edge of the shift clock

(TXD) so that an external device can latch the data using the rising edge of the shift clock.

The UART begins to receive data when the REN bit in the SCON register is set to logic 1 and the RI bit is set to logic 0. This condition

indicates that there is data to be shifted in on the Rx pin. The shift clock (TXD) is activated and data is latched on the rising edge. The

external device should therefore present data on the falling edge. This process continues until all eight bits have been received. The

RI bit is automatically set to logic 1, one clock cycle following the last rising edge of the shift clock on TXD. This causes reception to

stop until the SBUF has been read and the RI bit is cleared. When RI is cleared, another byte can be shifted in, if available.

8.5.2.2 UART Mode 1

This mode provides asynchronous, full-duplex communication. A total of 10 bits is transmitted, consisting of a start bit (logic 0), 8 data

bits, and 1 stop bit (logic 1), as illustrated in Figure 8-8. The data is transferred least significant bit first. The baud rate is programma-

ble through the baud-clock generator and is discussed later.

Following a write to SBUF, the UART begins transmission five clock cycles after the first baud clock from the baud-clock generator.

Transmission takes place on the Tx pin. It begins with the start bit being placed on the pin. Data is then shifted out onto the pin, least

significant bit first. The stop bit follows. The TI bit is set by hardware after the stop bit is placed on the pin. All bits are shifted out at

the rate determined by the baud clock generator.

Once the baud-clock generator is active, reception can begin at any time. The REN bit must be set to logic 1 to allow reception. The

detection of a falling edge on the Rx pin is interpreted as the beginning of a start bit, and begins the reception process. Data is shift-

ed in at the selected baud rate. At the middle of the stop bit time, certain conditions must be met to load SBUF with the received data

in the receive shift register:

RI must = 0, and either

if SM2 = 0, the state of the stop bit does not matter

or

if SM2 is 1, the state of the stop bit must be 1

If these conditions are true, the SBUF is loaded with the received byte, the RB8 bit is loaded with the stop bit, and the RI bit is set. If

these conditions are false, the received data is lost (SBUF and RB8 not loaded) and RI is not set. Regardless of the receive word sta-

tus, after the middle of the stop bit time, the receiver resumes looking for a 1-to-0 transition on the Rx pin.

Each data bit received is sampled on the 7th, 8th, and 9th clock used by the divide-by-16 counter. Using majority voting, two equal

samples out of the three determine the logic level for each received bit. If the start bit was determined to be invalid (= 1), the receive

logic resumes looking for a 1-to-0 transition on the Rx pin to start the reception of data.

8-25

__________________________________________________________________________________________________________

MAXQ7667 User’s Guide