10 fifo control register, 10 fifo control register (uart) (fcon) -12, Maxq7667 user’s guide – Maxim Integrated MAXQ7667 User Manual
Page 142: 10 fifo control register (uart) (fcon)
8.3.10 FIFO Control Register (UART) (FCON)
Register Description:
FIFO Control Register
Register Name:
FCON
Register Address:
Module 03h, Index 13h
Bit 7: Flush Transmit FIFO (FTF). If the host sets this bit to 1, the transmit FIFO pointer is reset to 0 and all transmit FIFO status flags
return to a value consistent with a system reset. Note that this does not affect the contents of the FIFO itself.
Bit 6: Flush Receive FIFO (FRF). If the host sets this bit to 1, the receive FIFO pointer is reset to 0 and all receive FIFO status flags
return to a value consistent with a system reset. Note that this does not affect the contents of the FIFO itself.
Bits 5 and 4: Transmit FIFO Threshold 1:0 (TXFT[1:0]). This field is used to select the “almost empty” threshold for the transmit FIFO.
In LIN slave mode, this field also determines the timing of the “partial frame transmitted” interrupt. The almost empty condition is set
according to the following table. Note that this field has no effect if the FIFO is disabled (FEN = 0).
Bits 3 and 2: Receive FIFO Threshold 1:0 (RXFT[1:0]). This field is used to select the “almost full” threshold for the receive FIFO. In
LIN master or LIN slave mode, this field also selects the timing of the “partial frame received” interrupt. The “almost full” condition is
set according to the following table. Note that this field has no effect if the FIFO is disabled (FEN = 0).
Bit 1: Overflow Error (OE). This bit is set to 1 by the peripheral when a byte of data is received and the receive FIFO is full.
Bit 0: FIFO Enable (FEN). This bit enables or disables the transmit and receive FIFO buffers. If this bit is set to 1, both FIFO buffers
are enabled. If this bit is cleared to 0, both FIFO buffers behave as though a single byte of storage is available.
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MAXQ7667 User’s Guide
r = read, w = write
Note: FCON is cleared to 00h on all forms of reset.
Bit #
7
6
5
4
3
2
1
0
Name
FTF
FRF
TXFT1
TXFT0
RXFT1
RXFT0
OE
FEN
Reset
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
TXFT[1:0]
INTERRUPT TIMING
00
The almost empty flag is never set by hardware. In LIN master or LIN slave mode, the partial frame transmitted interrupt is issued
when the transmit FIFO is full.
01
The almost empty flag is set and the partial frame transmitted interrupt is issued when the transmit FIFO is more than 25% full.
10
The almost empty flag is set and the partial frame transmitted interrupt is issued when the transmit FIFO is more than 50% full.
11
The almost empty flag is set and the partial frame transmitted interrupt is issued when the transmit FIFO is more than 75% full.
RXFT[1:0]
INTERRUPT TIMING
00
The almost full flag is never set by hardware. In LIN master or LIN slave mode, the partial frame received interrupt is issued when
the receive FIFO is full.
01
The almost full flag is set and the partial frame receive interrupt is when the receive FIFO is more than 25% full.
10
The almost full flag is set and the partial frame received interrupt is issued when the receive FIFO is more than 50% full.
11
The almost full flag is set and the partial frame received interrupt is issued when the receive FIFO is more than 75% full.