Maxim Integrated MAXQ7667 - Manual (Page 195)

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MAXQ7667 User’s Guide
11.4.1 Communication via TAP
The TAP controller is in test-logic-reset state after a power-on-reset. During this initial state, the instruction register contains bypass
instruction and the serial path defined between the TDI and TDO pins for the shift-DR state is the 1-bit bypass register. All TAP signals
(TCK, TMS, TDI, and TDO) default to being weakly pulled high internally on any reset. The TAP controller remains in the test-logic-reset
state as long as TMS is held high. The TCK and TMS signals can be manipulated by the host to transition to other TAP states. The TAP
controller remains in a given state whenever TCK is held low.
For the host to establish a specific data communication link, a private instruction must be loaded into the IR[2:0] register. Once the
instruction is latched in the instruction parallel buffer at the update-IR state, it is recognized by the TAP controller and the communi-
cation channel is established by putting the appropriate working register between TDI and TD0.
After a register has been placed between TDI and TDO, the in-circuit debug or in-system programming commands and data can be
exchanged between the host and the MAXQ7667 by operating in the data register portion of the state sequence (i.e., DR-scan). The
TAP retains the private instruction that was loaded into IR[2:0] until a new instruction is shifted in or until the TAP controller returns to
the test-logic-reset state. Essentially, the IR-scan sequence selects the appropriate registers between TDI and TDO for debug, in-sys-
tem programming, and bypass mode. Once the appropriate register is selected, the DR-scan sequence can be executed.
11.4.2 Test-Logic-Reset
On a power-on reset, the TAP controller is initialized to the test-logic-reset state and the instruction register (IR[2:0]) is initialized to the
bypass instruction so that it does not affect normal system operation. No matter what the state of the controller, it enters test-logic-reset
when TMS is held high for at least five rising edges of TCK. The controller remains in the test-logic-reset state if TMS remains high. An
erroneous low signal on the TMS can cause the controller to move into the run-test-idle state, but no disturbance is caused to system
operation if the TMS signal is returned and kept at the intended logic high for three rising edges of TCK since this returns the controller
to the test-logic-reset state.
11.4.3 Run-Test-Idle
As illustrated in Figure 11-2, the run-test-idle state is an intermediate state for getting to one of the two state sequences in which the
TAP controller performs meaningful operations:
• Controller state sequence (IR-scan)
• Data register state sequence (DR-scan)
11.4.4 IR-Scan Sequence
The MAXQ7667 supports a 3-bit TAP instruction register to allow certain device specific instructions (e.g., "Debug" or "System
Programming") to be supported. The IR-Scan sequence allows instructions (e.g., "Debug" and "System Programming") to be shifted
into the instruction register starting from the select-IR-scan state. In the TAP, the instruction register is connected between the TDI input
and the TDO output. Inside the IR-scan sequence, the capture-IR state loads a fixed binary pattern (001b) into the 3-bit shift register
and the shift-IR state causes shifting of TDI data into the shift register and serial output to TDO, least significant bit first. Once the
desired instruction is in the shift register, the instruction can be latched into the parallel instruction register (IR[2:0]) on the falling edge
of TCK in the update-IR state. The contents of the 3-bit instruction shift register and parallel instruction register (IR[2:0]) are summa-
rized with respect to the TAP controller states in Table 11-2.
Table 11-2. Instruction Register Content vs. TAP Controller State
TAP CONTROLLER STATE INSTRUCTION SHIFT REGISTER PARALLEL (3-BIT) INSTRUCTION REGISTER (IR2:IR0)
Test-Logic-Reset Undefined Set to bypass (011b) instruction
Capture-IR Load 001b at the rising edge of TCK Retain last state
Shift-IR
Input data via TDI and shift towards TDO at the rising
edge of TCK
Retain last state
Exit1-IR, Exit2-IR, Pause-IR Retain last state Retain last state
Update-IR Retain last state Load from shift register at the falling edge of TCK
All other states Undefined Retain last state