Maxim Integrated MAXQ7667 - Manual (Page 158)

8.5.2.3 UART Mode 2
This mode uses a total of 11 bits in asynchronous, full-duplex communication as illustrated in Figure 8-9. The 11 bits consist of one
start bit (a logic 0), 8 data bits, a programmable 9th bit, and one stop bit (a logic 1). Like mode 1, the transmissions occur on the Tx
signal pin and receptions on Rx.
For transmission purposes, the 9th bit can be stuffed as logic 0 or 1. A common use is to put the parity bit in this location. The 9th bit
is transferred from the TB8 bit position in the SCON register following a write to SBUF to initiate a transmission. The UART transmission
begins five clock cycles after the first rollover of the divide-by-16 counter following a software write to SBUF. It begins with the start bit
being placed on the Tx pin. The data is then shifted out onto the pin, least significant bit first, followed by the 9th bit, and finally the
stop bit. The TI bit is set when the stop bit is placed on the pin.
Once the baud-rate generator is active and the REN bit has been set to logic 1, reception can begin at any time. Reception begins
when a falling edge is detected as part of the incoming start bit on the Rx pin. The Rx pin is then sampled according to the baud rate
speed. The 9th bit is placed on the RB8 bit location in the SCON register. At the middle of the 9th bit time, certain conditions must be
met to load SBUF with the received data:
RI must = 0, and either
if SM2 = 0, the state of the 9th bit does not matter
or
if SM2 is 1, the state of the 9th bit must be 1
If these conditions are true, the SBUF is loaded with the received byte, the RB8 bit is loaded with the 9th bit, and the RI bit is set. If
these conditions are false, the received data is lost (SBUF and RB8 not loaded) and RI is not set. Regardless of the receive word sta-
tus, after the middle of the stop bit time, the receiver resumes looking for a 1-to-0 transition on the Rx pin.
Data is sampled in a similar fashion to mode 1 with the majority voting on three consecutive samples. Mode 2 uses the sample divide-
by-16 counter with either the system clock divided by 2 or 4, thus resulting in a baud clock of either system clock/32 or system clock/64.
8.5.2.4 UART Mode 3
This mode has the same operation as mode 2, except for the baud-rate source. As shown in Figure 8-10, mode 3 generates the baud
rates through the baud-clock generator. The bit shifting and protocol are the same. The baud-clock generator is discussed in another
section.
8.5.3 Framing Error Detection
A framing error occurs when a valid stop bit is not detected. This results in the possible improper reception of the serial word. The
UART can detect a framing error and notify the software. Typical causes of framing errors are noise and contention. The framing error
condition is reported in the SCON register for the UART.
The framing error bit, FE, is located in SCON. Note that this bit normally serves as SM0 and is described as SM0/FE in the register
description. Framing error information is made accessible by the FEDE (framing error detection enable) bit located at SMD.0. When
FEDE is set to logic 1, the framing error information is shown in SM0/FE (SCON). When FEDE is set to logic 0, the SM0 function is acces-
sible. The information for bits SM0 and FE is actually stored in different registers. Changing FEDE only modifies which register is
accessed, not the contents of either.
The FE bit is set to 1 when a framing error occurs. It must be cleared by software. Note that the FEDE state must be 1 while reading
or writing the FE bit. Also note that receiving a properly framed serial word does not clear the FE bit. This must be done in software.
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MAXQ7667 User’s Guide