Maxim Integrated MAXQ7667 - Manual (Page 300)

17.4.2.2 Configuring the Burst Variables
The Clock-Burst-In (Figure 17-1) is selected by the burst clock select bit, BCKS (BTRN.10). The Clock-Burst-In is the clock used to
generate the burst frequency (B FREQ ) and the Recv-Clock that feeds the echo reception section. If the BCKS bit is set to 1, the sys-
tem clock is selected; otherwise, if BCKS = 0 the programmable PLL oscillator is selected. The reset state sets BCKS to a 1, selecting
the system clock as the default.
If PLL is the source for the clock input, the PLL should be configured appropriately. The PLL clock-divide control bits, PLLC[1:0]
(PLLF.10:9), identify to the PLL the frequency of the crystal or resonator being used for the system clock. Table 17-4 shows the PLLC
settings and the corresponding SYSCLK.
Table 17-4. PLLC Settings to Identify the Frequency of the Crystal to the PLL Stage
While the MAXQ7667 processor can operate from a wide range of crystal frequencies, the PLL will not. If crystal/resonator frequencies
other than those specified in Table 17-4 are used, the PLL can attempt to lock to a frequency outside its designed range and may not
function correctly. If the system clock is the internal RC oscillator, make sure to set the RC oscillator to 16MHz; then setting the PLCC
bits to 0b00 selects this value correctly.
The PLL clock frequency is dictated by the equation:
PLL FREQ = SYSCLK x [(PLLF + 768)/1024]
where PLL FREQ is the output frequency and PLLF is a control value between 0 and 511, set in the PLLF.[8:0] register. This allows for
an adjustment of ±25% around the center frequency with a worst-case resolution of 1 part in 1024 or 0.1%.
The PLL clock undergoes further division (Figure 17-1), controlled by the burst divider bits BDIV[3:0] (BTRN.15:12). The BDIV bits are
not the actual divisor. See Table 17-5 for actual divisor values. The BDIV bits also divide the receive clock in the echo reception stage.
In Table 17-5, the Bdivisor is the actual divisor for the burst transmission stage, while the Rdivisor is the divisor for the receiver clock
for the echo reception stage. The Rdivisor value is transparent to the user.
Hence, if the PLL is used as the clock source, the frequency of the burst signal is given by:
B FREQ = [SYSCLK x (PLLF + 768)/(1024 x Bdivisor)]
If system clock, SYSCLK, is chosen as the clock source instead of the PLL, the SYSCLK is divided by the Bdivisor rather than the PLL.
Therefore, the frequency of the burst signal is given by:
B FREQ = (SYSCLK)/Bdivisor
The duty cycle of the burst signal is set by the burst pulse-width high bits, BPH[9:0]. The duty cycle is given by:
Duty Cycle = 100 x BPH/Bdivisor (see Table 17-5 for Bdivisor)
However, if Bdivisor ≤ BPH:
Duty Cycle = (Bdivisor - 1)/Bdivisor
A single burst has a number of whole cycles that can be programmed through the burst pulse count bits, BCNT.[7:0] (BTRN.7:0). BCNT
can be set to any value from 0 to 255, however one cycle is the smallest burst. The burst contains one cycle if BCNT = 0 or 1. If BCNT
= 255, the burst contains 255 cycles.
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MAXQ7667 User’s Guide
PLLC[1:0]
SYSCLK (XTAL/RESONATOR FREQUENCY)
(MHz)
00
(default)
16
01 8
10 4