Maxim Integrated MAXQ7667 - Manual (Page 114)

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MAXQ7667 User’s Guide
6.7.1 16-Bit Timer: Autoreload/Compare
The 16-bit autoreload/compare mode for the Type 2 timer is in effect when the timer-mode select bit (T2MD) is cleared and the cap-
ture/compare function definition bits are both cleared (CCF[1:0] = 00b). The timer value is contained in the T2Vx register. The timer run
control bit (TR2) starts and stops the 16-bit timer. The input clock for the 16-bit Type 2 timer is defined as the system clock divided by
the ratio specified by the T2DIV[2:0] prescale bits. The timer begins counting from the value contained in the T2Vx register until an
overflow occurs. When an overflow occurs, the reload value is reloaded instead of the x0000h state. The timer overflow flag (TF2) is
set every time that an overflow condition (T2Vx = 0xFFFFh) is detected. If the Type 2 timer interrupts have been enabled (ET2 = 1), the
TF2 flag can generate an interrupt request. When operating in compare mode, the capture/compare register, T2Cx, is compared ver-
sus the timer value registers. Whenever a compare match occurs, the capture/compare status flag (TCC2) is set. If the Type 2 timer
interrupts have been enabled (ET2 = 1), this event can generate an interrupt request. If the capture/compare register is set to a value
outside of the timer counting range, a compare match is not signaled and the TCC2 flag is not set. Internally, a timer output clock is
generated that toggles on the cycle following any compare match or overflow, unless the compare match value has been set equal to
the overflow condition, in which case, only one toggle occurs. This clock is sourced out on the designated timer/counter pins of the
microcontroller.
• Output Enable (PWM Out). The output enable bits (T2OE[1:0]) enable the timer output clock to be presented on the pins asso-
ciated with the respective bits. If the Type 2 timer has a single I/O pin, as in the case of timer 1, the T2OE0 bit is associated
with the T2Px pin and the T2OE1 bit is not implemented (as it would serve no purpose as in the case of timer 1).
• Polarity Control. The polarity control bits (T2POL[1:0]) can be used to modify (invert) the enabled clock outputs to the pin(s).
The enabled clock outputs (defined by T2OE[1:0]) will toggle on each compare match or overflow. The T2POL[1:0] bits are log-
ically XORed with the timer output signal, therefore setting a given T2POLn bit will result in a high starting state. The T2POLn
bit can be changed any time, however, the assigned T2POLn state will take effect on the external pin only when the corre-
sponding T2OEn bit is changed from 0 to 1. (Timer 1 has no secondary pin, hence polarity control is not available.)
• Gated. To use the T2P pin as a timer input clock gate, the T2OE0 bit must be cleared to 0, i.e., it is an input, and the G2EN bit
must be set to 1. When T2OE0 = 1, the G2EN bit setting has no effect. When T2OE0 is cleared to 0, the respective polarity con-
trol bit is used to modify the polarity of the input signal to the timer. In the gated mode, the timer input clock is gated anytime
the external signal matches the state of the T2POL0 bit. This means that the default clock gating condition for the T2P pin is
logic low (since T2POL0 = 0 default). Setting T2POL0 = 1 results in the timer input clock being gated when the T2P pin is high.
Note that if multiple pins are allocated for the Type 2 timer (i.e., T2P, T2PB), the primary pin can be used for clock gating, while
the secondary pin can be used to output the gated PWM output signal (if T2OE1 = 1).
• Single-Shot (and Gating). When operating in 16-bit compare mode, the single-shot is used to automate the generation of sin-
gle pulses under software control or in response to an external signal (single-shot gated). To generate single-shot output puls-
es solely under software control, the G2EN bit should be cleared to 0, the output enables and polarity controls should be con-
figured as desired, and the single-shot bit should be set to 1. Writing the single-shot bit effectively overrides the TR2 = 0 con-
dition until timer overflow/reload occurs. The single-shot bit is automatically cleared once the overflow/reload occurs.
Writing SS2 and TR2 = 1 at the same time still causes the SS2 bit to stay in effect until an overflow/reload occurs, however, since
TR2 was also written to a 1, the specified PWM output continues even after SS2 becomes clear.
If two pins are available for the Type 2 timer implementation, an additional mode is supported: single-shot gated. Single-shot
gated requires that the T2P pin be used as an input (T2OE0 = 0). It also requires that G2EN = 1, thus differentiating it from the
software-controlled single-shot mode on the second output pin. If G2EN is enabled and SS2 is written to 1, the gating condi-
tion must first be removed in order for the single-shot enabled output to occur on the pin. When the clock gate is removed, the
single-shot output occurs. Just as previously described, the SS2 bit = 1 state remains in effect until overflow/reload. Note that
this makes it possible for the single-shot to span multiple gated/nongated intervals. Once the SS2 = 1 conditions completes, if
TR2 = 1, the gated PWM mode is in effect. Otherwise (TR2 = 0), the timer is stopped.
• Capture/Reload Control. For the 16-bit compare operating mode, the CPRL2 bit is not used.