Maxim Integrated MAXQ7667 - Manual (Page 115)

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MAXQ7667 User’s Guide
6.7.2 16-Bit Timer: Capture Mode
The 16-bit capture mode requires that some event trigger the capture. Normally, this event will be an external edge. The CCF[1:0] bits
define which edge(s) causes a capture to occur. If CCF[1:0] = 01b, a rising edge causes a capture. If CCF[1:0] = 10b, a falling edge
causes a capture. If CCF[1:0] = 11b, rising and falling edges both cause a capture to occur. The CPRL2 bit enables both capture and
reload to occur on the specified edge(s).
• Output Enable. In 16-bit capture mode, the output enables are meaningless. No output waveform is allowed since the cap-
ture/compare registers are being used for the purpose of capturing the timer value.
• Polarity Control. The polarity control bits (T2POL[1:0]) have no specific meaning as related to the output function since there
is no output function. The T2POL0 bit is used to establish the gating condition for the single-edge capture mode when gating
is enabled (G2EN = 1). If capture and reload are defined (CPRL2 = 1 and CCF[1:0] = 11b) for both edges, the T2POL0 bit can
be used to specify which edge does not have an associated edge reload when gating has also been enabled (G2EN bit = 1).
When the SS2 bit is used to delay the timer run (for both edge capture), the T2POL0 bit also defines which edge starts/ends
the single-shot process.
• Edge Detection. Edge detection was described above (CCF[1:0] controlled).
• Gated. If gating is specified, it uses the T2POL0 bit to define when the input clock to the timer is gated (just as described for
the compare mode). This mode can easily be used to measure or incrementally capture high or low pulse durations. If a pre-
defined high/low duration is required to generate an interrupt, the gated compare mode can also be used. Note that if capture
is defined for both rising and falling edges, gating would serve no useful purpose because it would result in redundant capture
data/interrupts. For this reason, when G2EN = 1 and CCF[1:0] = 11b, the T2POL0 bit is used to specify which edge is a cap-
ture-only edge when CPRL2 = 1 (gating of the reload event).
• Single-Shot. The single-shot bit overrides the TR2 = 0 bit setting for a single edge-to-edge capture cycle (as defined by the
CCF[1:0] bits). The single-shot takes effect (starting the timer) only when 1) the edge defined by CCF[1:0] is detected or 2) the
defined gating condition is removed. While a capture and/or reload may occur on this starting edge, the interrupt flag will not
be set since a single-shot event has been requested. When rising or falling edge capture is defined, the single-shot mode is
useful for measuring single periods. If gating is also specified for the single-shot, the high/low pulse widths are easily measured.
If rising and falling edges are defined, the T2POL0 bit designates which edge starts/ends the single-shot cycle, but the start-
ing edge will not cause the interrupt flag to set. If G2EN = 1 for the two-edge capture, the alternate edge (opposite of defined
start/end edge can only be used for capture, not capture and reload). For T2POL0 = 1, the falling edge starts and stops the
single shot. This is important for combined duty cycle and period measurement.
• Capture and Reload. The CPRL2 bit enables both capture and reload on the specified edge(s). The only exception to this rule
is when the G2EN bit is set to a logic 1. When G2EN is set to 1, a reload does not occur on the edge specified by T2POL0.
When T2POL0 = 0, the falling edge does not cause a reload; if T2POL0 = 1, the rising edge does not cause a reload.
6.7.3 16-Bit Counter
The 16-bit counter mode is enabled by setting the C/T2 bit to logic 1. When C/T2 = 1, rising, falling, or both rising and falling edges
are counted as determined by the CCF[1:0] bits. If CCF[1:0] = 00b, neither edge is defined as a counted edge, and the T2Vx counter
will hold its count since no edge is defined as the counting edge. When an overflow occurs, the reload value (T2Rx) is reloaded instead
of the x0000h state. The timer/counter 2 overflow flag (TF2) is set every time that an overflow occurs. If timer/counter 2 interrupts have
been enabled (ET2 = 1), the TF2 flag can generate an interrupt request. In counter mode, the capture/compare register (T2Cx) is com-
pared versus the timer/counter 2 value register. Whenever a compare match occurs, the capture/compare status flag (TCC2) is set. If
timer/counter 2 interrupts have been enabled (ET2 = 1), this event can generate an interrupt request. If the capture/compare register
is set to a value outside of the Type 2 timer counting range, a compare match is not signaled and the TCC2 flag is not set.
• Output Enable. For the timer to serve as a counter, the T2Px pin must be used as an input. Thus, when C/T2 = 1, the T2OE0
bit is ignored. The T2OE1 bit can be used to output the generated waveform on T2PB (not available for timer 1) resulting from
compare match and overflow conditions for the counter.
• Polarity Control. Only the T2POL1 bit is meaningful. It can define the starting state of the T2PBx pin when the T2PB output has
been enabled. The T2POL1 bit can be changed any time, however, the assigned T2POL1 state will take effect on the external
pin only when the corresponding T2OE1 bit is changed from 0 to 1.
• Gating and Single-Shot. Neither gating nor single-shot modes are supported when operating in 16-bit counter mode. The
G2EN and SS2 bits should not be set to 1 when operating in the counter mode (C/T2 = 1).