Maxim Integrated MAXQ7667 - Manual (Page 249)

14-17 _________________________________________________________________________________________________________
MAXQ7667 User’s Guide
Figure 14-8 shows single-edge-controlled ADC conversion timing when the ADC is in auto shutdown state. The power-up and acqui-
sition is triggered by the falling edge of the ADC conversion start source signal ADC_CNVST. ADC_CNVST is an internal signal gen-
erated from a combination of all the three conversion start sources previously described.
In single-edged conversions, the ADC control logic provides the necessary power-up, acquisition, and conversion delay.
a) If ADC is in auto shutdown state, it takes a total of 27 ADC clock cycles before the 12-bit result is available.
b) If ADC is not in auto shutdown state, it takes a total of 17 ADC clock cycles before the 12-bit result is available.
Figure 14-9 shows single-edge-controlled ADC conversion when the ADC is not in auto shutdown state.
Table 14-5. ADC Dual- and Single-Edge Modes (continued)
ADC DUAL-
MODE
(SARDUL)
ADC CONVERSION
SOURCE
(SARS[2:0])
ADC CONVERSION
TRIGGER
ADC CONVERSION DESCRIPTION
110
(Continuous)
Write 110 to
SARS[2:0]
Write 110 to SARS[2:0]
• If in auto shutdown, logic requires 8 cycles to power up.
• Sets T/H into track mode.
• ADC control logic provides the required track duration.
• T/H placed in hold after 3 clock cycles.
• Then SAR conversion executes (13 ADC clock cycles).
Conversion continuously repeated every 16 ADC clock cycles. 0
(Single-Edge
Mode)
111
(Start/Busy bit)
Write 1 to SARBY
(Start/Busy Bit)
Write 1 to Start/Busy Bit
• Sets T/H into track mode.
• ADC control logic provides the required track duration composed of power-up
delay (10 cycles), acquisition delay (3 cycles), and settling delay.
• If ADC is in auto shutdown, T/H placed in hold after 11 clock cycles.
• If ADC is not in auto shutdown, T/H placed in hold immediately.
• Then SAR conversion executes (13 ADC clock cycles).
Figure 14-8. Single-Edge ADC Conversion Timing; ADC Previously Off
1 17 27 13
SARBY
ADCDATA
ADCCLK
ADC_CNVST
DATA (n-1) DATA (n)
ACQUISITION (n)
POWER-UP CONVERSION (n)